During the manufacture of semiconductor devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), microprocessors, logic, etc., several structures are commonly formed. With reference to FIG. 1, a semiconductor wafer substrate assembly 10 is provided. The wafer assembly typically comprises a semiconductor wafer 12 having a transistor stack 14 formed thereon. With current technology, for example a 64 megabit DRAM manufactured with 0.18-micron line widths, each wafer stack comprises gate oxide 16 about 60 angstroms (Å) thick, a polysilicon control gate (word line) 18 about 800 Å thick, a silicide layer 20 about 1,000 Å thick, a nitride cap 22 about 2,000 Å thick, and a pair of oxide spacers 24. The spacing between each stack (between adjacent spacers) is about 1,300 Å. Such a structure is easily manufactured by one of ordinary skill in the art.
FIG. 1 further depicts a doped blanket polysilicon layer 26, for example about 3,500 Å thick which is provided to form a landing pad for a contact. A patterned photoresist mask 28 is formed over the polysilicon layer 26 and an anisotropic polysilicon etch is performed to define the landing pad. To etch the polysilicon layer depicted, a conventional etch comprises 90 standard cubic centimeters (sccm) Cl2 and 10 sccm NF3 at a pressure of 300 millitorr (mTorr) and 100 watts power to clear the majority of the exposed polysilicon, then the pressure is increased and SF6 is added toward the end of the etch in an attempt to clear any residual material from the exposed regions.
A desired resulting structure is depicted in FIG. 2 which depicts a clean removal of the exposed polysilicon and no undercutting of the resist. However, with severe topology having narrow spaces between the relatively high transistor gate stacks, a more common result is depicted in FIG. 3. Stringers 30 can form in the recesses as it is difficult to clear all the polysilicon from narrow, deep spaces found with high-density semiconductor devices, even with the increase in pressure and addition of SF6 in the conventional etch described above. Stringers, which form especially in corners, are well known in the art to cause shorting and result in malfunctioning semiconductor devices.
Another method used in an attempt to reduce stringers includes performing a series of alternating anisotropic and isotropic etches, with the anisotropic etches removing the polysilicon in a substantially vertical direction and the isotropic etches removing the polysilicon in both horizontal and vertical directions. One problem with this method is that the isotropic etches undercut the photoresist 28 and narrow the width of the polysilicon feature 26. Thus the critical dimension (CD) of the polysilicon feature is wider than would be required if the photoresist was not undercut, and thus the alignment tolerance is reduced. For example, with a device using 0.18 micron line widths a typical undercut is about 0.03 microns on each side (0.06 microns total). Thus the feature must be patterned for a 30% undercut tolerance. The additional space required for this allowance is a concern especially as the number of features on the device increases.
As device generations progress, the spaces between transistor stacks will decrease thereby exacerbating the problem of remaining stringers. A method which removes polysilicon, and particularly which removes stringers from severe topology, would be desirable.